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| [[Category:INES Mappers|006]][[Category:Mappers with cycle IRQs]] | | {{DEFAULTSORT:006}}[[Category:INES Mappers]][[Category:Mappers with cycle IRQs]] |
| iNES Mappers 006/008 are used for ROM images that have been converted from disk images for the ''Bung Game Doctor'' copiers. It is also supported by the ''Front FarEast Super Magic Card'' copiers. All of these ROM images have been extensively modified to use the copier's idiosyncratic bankswitch registers. | | '''iNES Mapper 006''' denotes ROM images that have been extracted from disk images for the ''Front Fareast Magic Card 1M'' or ''2M'' [[RAM cartridge|RAM cartridges]]. They represent games whose [[Game_Doctor/Magic_Card_FDS_Format#Front_Fareast_Magic_Card_1M.2F2M.2F4M_disks|Doctor Header file]] denotes a Magic Card 1M/2M disk (byte $0 bit 7 set, bits 4 and 5 clear, byte $7=$00). Refer to the [[Super Magic Card]] article for details on bankswitching. The Super Magic Card's registers are initialized to: |
| | ; Play mode, WRAM bank 0, 1 KiB CHR mode disabled |
| | [[Super_Magic_Card#Super_Magic_Card_mode_.28.244500.2C_write-only.29|$4500]] = $42 |
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| | ; PRG memory write-protected, two-screen mirroring |
| | [[Super_Magic_Card#1M_banking_mode_.28.2442FC-.2442FF.2C_write-only.29|$42FF]] = (submapper <<5) | (verticalMirroring? 0x00: 0x10) |
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| | ; 2M/4M banking mode disabled |
| | [[Super_Magic_Card#2M.2F4M_PRG_banking_mode_.28.2443FC-.2443FF.2C_write-only.29|$43FF]] = $00 |
| | The [[NES 2.0]] Submapper field denotes the initial [[Super_Magic_Card#Latch-based_modes|latch-based banking mode]] (0-7). [[INES|NES 1.0]] files correspond to submapper 1. '''iNES [[INES Mapper 008|Mapper 8]]''' is a synonym of Mapper 6 submapper 4. |
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| There are 32 KiB of CHR-RAM, enough to run games with less than or equal to that amount of CHR data with little modification. For games with more than 32 KiB of CHR-ROM, additional bankswitching code keeps track of the game's CHR-ROM bank usage and caches the most recently-used 32 KiB in CHR-RAM, copying data from PRG address space into CHR-RAM as needed. This necessarily involves screen flicker. The amount of extra code needed to accomplish requires a "trainer" that is always loaded into PRG-RAM at $7000. According to the [[iNES]] format, this Trainer is supposedly always 512 bytes in size. A few ROM images however actually have 640- or 768-byte trainers, whose size must be detected as the modulus 8192 of the file size minus the 16 byte iNES header, detecting and ignoring any footer.
| | The [[iNES]] header may specify a [[INES#Trainer|512-byte trainer]] (corresponding to [[Game_Doctor/Magic_Card_FDS_Format#Front_Fareast_Magic_Card_1M.2F2M.2F4M_disks|Doctor Header file]]'s byte $0 bit 6 being set), which must be loaded to $7000-$71FF, be writable, and (on a hard reset) initialized by JSRing to $7003 before JMPing to the game's reset vector. |
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| =Banking Modes=
| | Battery-saving of WRAM content is not supported by any Magic Card model. Hard-resetting a game while restoring previously-saved WRAM content in emulators interferes with the correct operation of the trainer's program. |
| The banking mode is changed via registers $42FE/$42FF. The initial banking mode upon startup would be directly available in the original disk image format that these copiers used, but can only be roughly deduced from the iNES header:
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| * Mapper 002: Either actual [[INES Mapper 002]] (UNROM/UOROM) or Copier Modes 0 (128 KiB PRG) or 2 (256 KiB PRG). Since actual UNROM/UOROM boards do not have PRG-RAM, any Mapper 002 iNES-format ROM image that has the Battery bit set, the Trainer bit set, or writes to $4024-$43FF is actually a Copier Mode 0/2 game.
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| * Mapper 003: Either actual [[INES Mapper 003]] (CNROM) or Copier Modes 5 (32 KiB CHR) or 7 (16 KiB CHR). Since actual CNROM boards do not have PRG-RAM, any Mapper 003 iNES-format ROM image that has the Battery bit set, the Trainer bit set, or writes to $4024-$43FF is actually a Copier Mode 5 game.
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| * Mapper 006: Unspecified, but almost always Copier Mode 1.
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| * Mapper 008: Copier Mode 4.
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| The initial nametable mirroring type can be deduced from the iNES header. Gmes that require one-screen mirroring, which could not be conveyed by the iNES header, always enable it by writing to $42FE themselves.
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| ==Mode 0: UNROM== | | =See also= |
| * 16 KiB PRG-ROM bank at CPU $8000-$BFFF, switched by D0..D7 of data latch at CPU $8000-$FFFF
| | * [//nesdev.org/mapper6.txt Mapper 6] Info on the FFE mapper. By FanWen Yang (outdated). |
| * 16 KiB PRG-ROM bank at CPU $C000-$FFFF, fixed to bank #7
| | * [http://www.famicomdisksystem.com/game-doctor-copiers/ Info on various Famicom "copiers"] |
| * 8 KiB of unbanked CHR-RAM
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| ==Mode 1: Custom==
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| * 16 KiB PRG-ROM bank at CPU $8000-$BFFF, switched by D2..D7 of data latch at CPU $8000-$FFFE (not $FFFF!)
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| * 16 KiB PRG-ROM bank at CPU $C000-$FFFF, fixed to bank #7
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| * 8 KiB CHR-RAM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFE (not $FFFF!)
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| ==Mode 2: UOROM==
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| * 16 KiB PRG-ROM bank at CPU $8000-$BFFF, switched by D0..D7 of data latch at CPU $8000-$FFFF
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| * 16 KiB PRG-ROM bank at CPU $C000-$FFFF, fixed to bank #15
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| * 8 KiB of unbanked CHR-RAM
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| ==Mode 3: Reverse UOROM==
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| * 16 KiB PRG-ROM bank at CPU $8000-$BFFF, fixed to bank #15
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| * 16 KiB PRG-ROM bank at CPU $C000-$FFFF, switched by D0..D7 of data latch at CPU $8000-$FFFF
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| * 8 KiB of unbanked CHR-RAM
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| * Seems to used by only one game (''Kaiketsu Yanchamaru'').
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| ==Mode 4: GNROM==
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| * 32 KiB PRG-ROM bank at CPU $8000-$FFFF, switched by D4..D5 of data latch at CPU $8000-$FFFF
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| * 8 KiB CHR-RAM/ROM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFF
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| ==Mode 5: CNROM (32 KiB CHR)==
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| * 32 KiB PRG-ROM bank at CPU $8000-$FFFF, fixed to bank #7
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| * 8 KiB CHR-RAM/ROM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFF
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| ==Mode 6: NROM-256/Protection==
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| * 32 KiB PRG-ROM bank at CPU $8000-$FFFF, fixed to bank #3
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| * 8 KiB of unbanked CHR-RAM
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| * Several ROM images set this mode to verify the content of a particular ROM location and will deliberately fail if it does not match.
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| ==Mode 7: CNROM (16 KiB CHR)/Protection==
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| * 32 KiB PRG-ROM bank at CPU $8000-$FFFF, fixed to bank #3
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| * 8 KiB CHR-RAM/ROM bank at PPU $0000-$1FFF, switched by D0 of data latch at CPU $8000-$FFFF
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| * Several ROM images set this mode to verify the content of a particular ROM location and will deliberately fail if it does not match.
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| ==4M Mode==
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| * 8 KiB PRG-ROM bank at CPU $8000-$9FFF, switched by D2..D7 of data latch at CPU $8000-$9FFF
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| * 8 KiB PRG-ROM bank at CPU $A000-$BFFF, switched by D2..D7 of data latch at CPU $A000-$BFFF
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| * 8 KiB PRG-ROM bank at CPU $C000-$DFFF, switched by D2..D7 of data latch at CPU $C000-$DFFF
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| * 8 KiB PRG-ROM bank at CPU $E000-$FFFF, switched by D2..D7 of data latch at CPU $E000-$FFFF
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| * 8 KiB CHR-RAM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFF
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| * 4M mode is enabled by writing any value to $43FE and disabled by writing any value to $43FF. If enabled, it has precedence over the eight banking modes set via $42FE-$42FF.
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| * The four PRG bank registers are latched, even if not applied, when the 4M Mode is not active, and will take effect once $43FE is written to afterwards.
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| =Global registers=
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| ==Mirroring and 1M/2M Banking Mode ($42FC-$42FF)==
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| A~FEDC BA98 7654 3210 D~7654 3210
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| ------------------- ---------
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| 0100 0010 1111 11bM BBBM ....
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| |+----|||+------ Set nametable mirroring type
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| | ||| 0: One-screen, page 0
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| | ||| 1: One-screen, page 1
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| | ||| 2: Vertical
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| | ||| 3: Horizontal
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| +-----|||------- 0: Ignore BBB bits, don't change banking mode
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| ||| 1: Obey BBB bits, change banking mode
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| +++------- New banking mode if b==1 (see above)
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| ==4M Banking Mode Enable/Disable ($43FE-$43FF)==
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| A~FEDC BA98 7654 3210
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| -------------------
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| 0100 0011 1111 111M
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| +- Enable/Disable 4M Banking Mode
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| 0: Enable
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| 1: Disable
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| ==FDS Write Data ($4024)==
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| This register is not part of the copier, but part of the FDS RAM adapter that attaches to it. A few games abusing the FDS Disk Data IRQ for frame timing write any value to this register to acknowledge a pending IRQ.
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| ==FDS Control ($4025)==
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| This register is not part of the copier, but part of the FDS RAM adapter that attaches to it. A few games abuse the FDS Disk Data IRQ for frame timing. If bit 7
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| is set, the FDS RAM adapter will generate IRQs every 1,792 cycles of the 21.4772 MHz master clock, or after every 149+1/3 CPU cycles.
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| ==Cycle IRQ Counter Low Byte ($4100)==
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| This is the low byte of a '''16-bit''' counter that, if nonzero, is increased on every M2 cycle and raises an IRQ when the counter flips from $FFFF to $0000. Writing
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| to this register also acknowledges the IRQ.
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| ==Cycle IRQ Counter High Byte ($4101)==
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| This is the high byte of a '''16-bit''' counter that, if nonzero, is increased on every M2 cycle and raises an IRQ when the counter flips from $FFFF to $0000.
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| =Notes=
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| * Before control is transferred to the game's Reset handler vectored at $FFFC, the copier BIOS issues a JSR to $7003 if it finds a valid trainer there. This call is necessary to properly set up initial CHR-RAM content and bankswitching registers.
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| * If a Mapper 006 ROM image specifies more than 32 KiB of CHR-ROM, then either it is not actually for Mapper 006, or those CHR-ROM banks need to be appended right after the PRG-ROM data.
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| * At least one game (''Ganbare Goemon Kaiden'') has a trainer but also uses battery-backed RAM for saves. The startup routine (at $7003) moves the trainer to a safe location that the game does not use. To avoid overwriting saved game data, the trainer should therefore only be placed at $7000 if no SRAM file has been loaded.
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| =More Information=
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| * [http://nesdev.org/mapper6.txt Mapper 6] Info on the FFE mapper. By FanWen Yang. | |
| * [http://forums.nesdev.org/viewtopic.php?p=5111 SMC Header] in nesdev forum.
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| * [http://www.famicomdisksystem.com/game-doctor-copiers/ Info on various famicom copiers] | |
