File talk:Ntsc timing.png: Difference between revisions
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according to blargg's odd/even frame test, this skipped cycle should be arranged at the last ppu cycle of the pre-render scanline, and the idle cycle presented in the image should be a read (if odd + rendering enabled). | according to blargg's odd/even frame test, this skipped cycle should be arranged at the last ppu cycle of the pre-render scanline, and the idle cycle presented in the image should be a read (if odd + rendering enabled). | ||
--[[Special:Contributions/110.206.2.212|110.206.2.212]] 01:34, 10 December 2013 (MST) | --[[Special:Contributions/110.206.2.212|110.206.2.212]] 01:34, 10 December 2013 (MST) | ||
*One of the comments (at the lower-right) states that the skipped cycle is actually at y=261,x=340 (and circuit analysis confirms that this is when it happens); I'm not sure why it's shown the way it is on the diagram. --[[User:Quietust|Quietust]] ([[User talk:Quietust|talk]]) 05:23, 11 December 2013 (MST) | |||
Revision as of 12:23, 11 December 2013
the first green ppu cycle 0 on the visible scanline 0 seems to be misleading. according to blargg's odd/even frame test, this skipped cycle should be arranged at the last ppu cycle of the pre-render scanline, and the idle cycle presented in the image should be a read (if odd + rendering enabled). --110.206.2.212 01:34, 10 December 2013 (MST)
