File:Apu address.jpg: Difference between revisions
(The NES APU's address decoder, generating enables for all reads/writes within $4000-$401F. Of very special note are the 4 signals at the very top for readable registers at $4018 (pulse 0 output on D0-D3 and pulse 1 output on D4-D7), $4019 (triangle outpu) |
(it also overrides the noise channel's LFSR output and appears to also stop the triangle channel from being clocked; I don't know what it does to DPCM, but it's probably something similar) |
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The NES APU's address decoder, generating enables for all reads/writes within $4000-$401F. | The NES APU's address decoder, generating enables for all reads/writes within $4000-$401F. | ||
Of very special note are the 4 signals at the very top for readable registers at $4018 (pulse 0 output on D0-D3 and pulse 1 output on D4-D7), $4019 (triangle output on D0-D3, noise output on D4-D7), $401A (DPCM output on D0-D6), and a writable register at $401A ( | Of very special note are the 4 signals at the very top for readable registers at $4018 (pulse 0 output on D0-D3 and pulse 1 output on D4-D7), $4019 (triangle output on D0-D3, noise output on D4-D7), $401A (DPCM output on D0-D6), and a writable register at $401A (set triangle position to D0-D4, and lock channel outputs using D7); all 4 of these signals have an additional enable which seems to come from the vicinity of [[CPU pin out and signal description|pin 30]]. | ||
Source: http://uxul.org/~noname/chips/cpu-5/stitched/final/ http://uxul.org/~noname/chips/cpu-2/no-metal/stitched/final/ | |||
Latest revision as of 03:18, 11 May 2011
The NES APU's address decoder, generating enables for all reads/writes within $4000-$401F.
Of very special note are the 4 signals at the very top for readable registers at $4018 (pulse 0 output on D0-D3 and pulse 1 output on D4-D7), $4019 (triangle output on D0-D3, noise output on D4-D7), $401A (DPCM output on D0-D6), and a writable register at $401A (set triangle position to D0-D4, and lock channel outputs using D7); all 4 of these signals have an additional enable which seems to come from the vicinity of pin 30.
Source: http://uxul.org/~noname/chips/cpu-5/stitched/final/ http://uxul.org/~noname/chips/cpu-2/no-metal/stitched/final/
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