User:Zzo38/Mapper F: Difference between revisions
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== Registers == | == Registers == | ||
Registers are mapped at $5800-$5FFF, using the low four bits as a register number. There may be different registers for reading as for writing. | Registers are mapped at $5800-$5FFF, using the low four bits as a register number. There may be different registers for reading as for writing. The same registers are also mapped at $1800-$1FFF, however reading from those address may result in bus conflicts. Writing there is OK, though. | ||
Therefore, the address mask is: | |||
[0.01 1... .... xxxx] | |||
=== $5800 (W) === | === $5800 (W) === | ||
[. | [ESMM CCCC] | ||
|||| |||| | |||
|||| ++++--- CIRAM enable | |||
||++-------- Nametable mirroring | |||
|+---------- CIRAM swap | |||
+----------- Enable console audio | |||
If the "E" bit is cleared, then only the expansion audio is played, and the audio from 2A03 + microphone is disabled. | |||
Nametable mirroring decides the connection of CIRAM A10, depending on "MM", and then that address line is XORed by "S", as follows: | |||
* 00 = PA10 | |||
* 01 = PA11 | |||
* 10 = PA12 | |||
* 11 = PA13 | |||
The "CCCC" decides which sections of PPU address space are accessing CIRAM (if the bit is clear, CIRAM is used; if set, the CHR ROM/RAM in the cartridge is used): | |||
* bit0 = $0000-$0FFF | |||
* bit1 = $1000-$1FFF | |||
* bit2 = $2000-$2FFF | |||
* bit3 = $3000-$3EFF | |||
=== $5800 (R) === | === $5800 (R) === | ||
This register is a | [.... XXXX] | ||
|||| | |||
++++--- 4-bit ADC | |||
This register is a 4-bit ADC for the 2A03+microphone audio. Mute and expansion audio are not applied; it is the same audio signal as cartridge is receiving at first. | |||
=== $5801 (W) === | |||
[VV.P PPPP] | |||
|| | |||| | |||
|| +-++++--- 16K PRG ROM bank at $8000-$BFFF | |||
++---------- Video mode | |||
=== $ | === $5802 (W) === | ||
[...P PPPP] | |||
| |||| | |||
+-++++--- 8K PRG ROM bank at $C000-$DFFF | |||
This is actually the low 8K of a 16K bank, so the high 8K of a 16K bank cannot be mapped into $C000-$DFFF. | |||
=== $5803 === | === $5803 === | ||
=== $5804 === | === $5804 === | ||
Same as register $580C, but for channel 1. | |||
=== $5805 === | === $5805 === | ||
Same as register $580D, but for channel 1. | |||
=== $5806 === | === $5806 === | ||
Same as register $580E, but for channel 1. | |||
=== $5807 === | === $5807 === | ||
=== $5808 === | === $5808 === | ||
Same as register $580C, but for channel 2. | |||
=== $5809 === | === $5809 === | ||
Same as register $580D, but for channel 2. | |||
=== $580A === | === $580A === | ||
Same as register $580E, but for channel 2. | |||
=== $580B === | === $580B === | ||
=== $580C === | === $580C (W) === | ||
[P..W AAAA] | |||
| | |||| | |||
| | ++++--- AND mask | |||
| +-------- Waveform (0: saw, 1: square) | |||
+----------- Phase reset if bit is cleared | |||
=== $580D === | === $580D (W) === | ||
[XXXX XXXX] | |||
|||| |||| | |||
++++-++++--- Low bits of period of channel 3 | |||
=== $580E === | === $580E (W) === | ||
[XXXX XXXX] | |||
|||| |||| | |||
++++-++++--- High bits of period of channel 3 | |||
=== $580F === | === $580F === | ||
Revision as of 05:26, 26 December 2013
Registers
Registers are mapped at $5800-$5FFF, using the low four bits as a register number. There may be different registers for reading as for writing. The same registers are also mapped at $1800-$1FFF, however reading from those address may result in bus conflicts. Writing there is OK, though.
Therefore, the address mask is:
[0.01 1... .... xxxx]
$5800 (W)
[ESMM CCCC] |||| |||| |||| ++++--- CIRAM enable ||++-------- Nametable mirroring |+---------- CIRAM swap +----------- Enable console audio
If the "E" bit is cleared, then only the expansion audio is played, and the audio from 2A03 + microphone is disabled.
Nametable mirroring decides the connection of CIRAM A10, depending on "MM", and then that address line is XORed by "S", as follows:
- 00 = PA10
- 01 = PA11
- 10 = PA12
- 11 = PA13
The "CCCC" decides which sections of PPU address space are accessing CIRAM (if the bit is clear, CIRAM is used; if set, the CHR ROM/RAM in the cartridge is used):
- bit0 = $0000-$0FFF
- bit1 = $1000-$1FFF
- bit2 = $2000-$2FFF
- bit3 = $3000-$3EFF
$5800 (R)
[.... XXXX]
||||
++++--- 4-bit ADC
This register is a 4-bit ADC for the 2A03+microphone audio. Mute and expansion audio are not applied; it is the same audio signal as cartridge is receiving at first.
$5801 (W)
[VV.P PPPP] || | |||| || +-++++--- 16K PRG ROM bank at $8000-$BFFF ++---------- Video mode
$5802 (W)
[...P PPPP]
| ||||
+-++++--- 8K PRG ROM bank at $C000-$DFFF
This is actually the low 8K of a 16K bank, so the high 8K of a 16K bank cannot be mapped into $C000-$DFFF.
$5803
$5804
Same as register $580C, but for channel 1.
$5805
Same as register $580D, but for channel 1.
$5806
Same as register $580E, but for channel 1.
$5807
$5808
Same as register $580C, but for channel 2.
$5809
Same as register $580D, but for channel 2.
$580A
Same as register $580E, but for channel 2.
$580B
$580C (W)
[P..W AAAA] | | |||| | | ++++--- AND mask | +-------- Waveform (0: saw, 1: square) +----------- Phase reset if bit is cleared
$580D (W)
[XXXX XXXX] |||| |||| ++++-++++--- Low bits of period of channel 3
$580E (W)
[XXXX XXXX] |||| |||| ++++-++++--- High bits of period of channel 3
