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| V.R. Technology's NES-on-a-chip consoles feature enhance the original NES/Famicom in several aspects.
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| = New Features =
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| == VT02+ Features ==
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| * OneBus mode: PRG and CHR data come from the same address space. The cartridge connector's PPU Address lines are repurposed as higher-order CPU Address lines.
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| * Integrated MMC3-compatible bankswitching by the console, active when in OneBus mode.
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| * Ability to use NTRAM as CHR-RAM.
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| * Choice of A12 and HBLANK as a source for clocking the scanline interrupt.
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| * Automatic X/Y light gun position determination.
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| * Integrated RS232 interface.
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| * Direct NTSC/PAL and 50/60 Hz identification.
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| * Automatic per-attribute-tile background and per-sprite sprite bankswitching.
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| * DMA can be used to transfer data to PPU memory (via $2007) in addition to the normal transferring of data to OAM memory (via $2004).
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| * A second APU doubling the number of sound channels.
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| * Raw PCM output using full eight bits of resolution.
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| * DMA-driven raw PCM output.
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| * Data for DMA-driven DPCM/PCM output can be placed anywhere in CPU address space, not just within the $C000-$FFFF range.
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| == VT03+ Features ==
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| * Sprites can be 16 pixels wide.
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| * Graphics can be in four-bits-per-pixel format in addition to the regular two-bits-per-pixel format.
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| * Enhanced color palette with twelve bits per color.
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| == VT16+ Features ==
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| * Internal CPU RAM is 4 KiB rather than just 2 KiB.
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| * The CPU can be set to run at the same speed (5.37 MHz) as the PPU.
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| * The CPU can be set to retrieve interrupt vectors from RAM ($0FFx) rather than ROM ($FFFx).
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| * DMA-driven DPCM/PCM output can be set to use its own banking registers independent of normal PRG banking.
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| * Hardware random number generator.
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| In this description, features are assigned to the earliest console type for which a datasheet is publicly available. The publicly-available datasheets are for the VT01, VT02, VT03, VT16 and VT18. Therefore, a feature described as VT16+ may have been available earlier on VT04 to VT15 consoles.
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| = Memory Map =
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| == CPU Memory Map ==
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| CPU $0000-$07FF: 2 KiB of internal RAM
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| CPU $0800-$0FFF: VT16+: VT01-VT03: Mirror of CPU $0000-$07FF, VT09+: Further 2 KiB of internal RAM
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| CPU $1000-$1FFF: Mirror of CPU $0000-$0FFF
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| CPU $2000-$2007: Famicom-compatible PPU registers
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| CPU $2010-$201F: New PPU registers
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| CPU $4000-$401F: Famicom-compatible APU, DMA and I/O registers
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| CPU $4020-$403F: New APU, DMA and I/O registers
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| CPU $4100-$41FF: New miscellaneous registers
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| CPU $6000-$7FFF: Optional WRAM, if present on cartridge
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| CPU $8000-$FFFF (write): When forwarding is enabled (see register $410B): MMC3-compatible registers that are forwarded to $4101-$4108)
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| CPU $8000-$FFFF (read): Four 8 KiB PRG-ROM banks. See the section "PRG ROM Bankswitching" for details.
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| == PPU Memory Map ==
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| * PPU $0000-$1FFF: CHR-ROM/CHR-RAM: VT03+ in 4 bits-per-pixel modes: bits 0 and 1 of each pixel
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| * PPU $2000-$2FFF: VRAM
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| * PPU $3F00-$3F7F: CGRAM, lower six bits of each color
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| * PPU $3F80-$3FFF: VT03: CGRAM, upper six bits of each color (only used if $2010 bit 7=1)
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| * PPU $4000-$5FFF: VT03+ in 4 bits-per-pixel modes: oCHR-ROM/CHR-RAM bits 2 and 3 of each pixel
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| = PRG-ROM Bankswitching =
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| The bankswitching scheme is based on, and indeed backwards-compatible, the Nintendo [[MMC3]]'s. The CPU address range is divided into four 8 KiB banks. For each of these four 8 KiB banks, the bank number is made up of three components:
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| * an Inner Bank that resembles the MMC3's bank registers,
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| * a Middle Bank that can replace zero to seven bits of the lower bank number,
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| * an Outer Bank that extend the address range up to 32 MiB.
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| == Inner Bank ==
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| The lower bits 8 KiB PRG-ROM bank number are normally the only ones that are manipulated by individual games. They select the Inner Bank and resemble the MMC3's original bank registers. By default, two of the four banks are fixed as on the MMC3; by setting bit 6 in register $410B (PQ2EN), the $C000-$DFFF bank may be turned into a selectable bank.
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| CPU $8000-$9FFF: Selected by register $4107 (PQ0), akin to MMC3 register 6.
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| CPU $A000-$BFFF: Selected by register $4108 (PQ1), akin to MMC3 register 7.
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| CPU $C000-$DFFF: If $410B bit 6 (PQ2EN)=0: Fixed to $FE, or second-to-last bank (within the Middle/Outer Bank), as on the MMC3.
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| If $410B bit 6 (PQ2EN)=1: Selected by register $4109 (PQ2), an enhancement over the MMC3.
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| CPU $E000-$FFFF: Fixed to $FF, or last bank (within the Middle/Outer Bank), as on the MMC3.
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| If $4105 bit 6 (COMR6) is 1, then the $8000-$9FFF/$A000-$BFFF banks are swapped with the $C000-$DFFF/$E000-$FFFF banks, just as on the MMC3.
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| == Middle Bank ==
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| The Middle Bank is normally only used on multicarts. It allows masking off and replacing bits of the Inner Bank number, so that several games may be put into one Outer Bank. Bits 0-2 of register $410B (PS) select the AND mask that is applied to the Inner Bank number. Only the bits that have been masked off that way are then replaced with the respective bits from register $410A (PQ3):
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| $410B Inner Bank PQ3 Effective
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| bits 0-2 AND Mask AND Mask Inner Bank Size
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| -------- ---------- -------- ---------------
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| 0 3F C0 512 KiB
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| 1 1F E0 256 KiB
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| 2 0F F0 128 KiB
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| 3 07 F8 64 KiB
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| 4 03 FC 32 KiB
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| 5 01 FE 16 KiB
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| 6 00 FF 8 KiB
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| 7 FF 00 2048 KiB
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