Cartridge connector: Difference between revisions

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m (Created page with '==Pinout of 60-pin Famicom consoles and cartridges== ------- GND - |01 31| - +5V PRG A11 - |02 32| - M2 ...')
 
m (→‎Signal Descriptions: (Fixed up some HUGE grammar and spelling mistakes))
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* '''SYSTEM CLK''' : Main oscillator frequency output. It is only available on 72-pin connectors, and it's speed varies from NTSC to PAL machines.
* '''SYSTEM CLK''' : Main oscillator frequency output. It is only available on 72-pin connectors, and it's speed varies from NTSC to PAL machines.


* '''M2''' : Also called PHI2 in official docs. This is the CPU clock output. When this signal is high, this means the PRG buss adresses and datas are on a stable state and can be latched by external hardware. On reads, the data must be stable until this signal goes low.
* '''M2''' : Also called PHI2 in official docs. This is the CPU clock output. When this signal is high, this means the PRG bus addresses and datas are on a stable state and can be latched by external hardware. On reads, the data must be stable until this signal goes low.


* '''PRG R/W''' : The Read/Write signal output from the CPU. This signal is high on during CPU reads and low during CPU writes (switches from one mode to another only when M2 is low).
* '''PRG R/W''' : The Read/Write signal output from the CPU. This signal is high on during CPU reads and low during CPU writes (switches from one mode to another only when M2 is low).


* '''PRG A0..A14''' : Also called just A0..A14 in official docs, or CPU A0..A14 (to not confuse with adress outputs of [[mappers]] sharing the same number). This is the CPU adress busses. It is stable when M2 is high. Note that A15 exists, but is not directly available on the connector.
* '''PRG A0..A14''' : Also called just A0..A14 in official docs, or CPU A0..A14 (to not confuse with address outputs of [[mappers]] sharing the same number). This is the CPU address buses. It is stable when M2 is high. Note that A15 exists, but is not directly available on the connector.


* '''PRG D0..D7''' : Also called just D0..D7 in official docs, or CPU D0..D7. This is the CPU bidirectionnal data bus. It goes high impedence on reads, allowing external memoriy chips to place their data here.
* '''PRG D0..D7''' : Also called just D0..D7 in official docs, or CPU D0..D7. This is the CPU bidirectional data bus. It goes high impedence on reads, allowing external memory chips to place their data here.


* '''PRG /CE''' : Also called /ROMSEL in official docs, to not confuse with PRG /CE output of mappers. This pins outputs logical NAND between M2 and PRG A15. It is low when the CPU reads or writes to $8000-$FFFF and when the adress is stable, allowing to enable ROM chips directly. Advanced [[mappers]] uses more logic between this pin and the actual PRG /CE (to disable [[bus conflics]], for example). Using this signal is the only way to determine the state of A15, so it's needed for any mappers doing any adress decoding.
* '''PRG /CE''' : Also called /ROMSEL in official docs, to not confuse with PRG /CE output of mappers. This pins outputs logical NAND between M2 and PRG A15. It is low when the CPU reads or writes to $8000-$FFFF and when the address is stable, allowing to enable ROM chips directly. Advanced [[mappers]] uses more logic between this pin and the actual PRG /CE (to disable [[bus conflicts]], for example). Using this signal is the only way to determine the state of A15, so it's needed for any mappers doing any address decoding.


* '''/IRQ''' : Interrupt request input. Input a low state to trigger an interrupt to the CPU. Can only be connected to an open collector cartridge output (there is an internal pullup resistor in the NES/Famicom). Can be left floating if interupts aren't used.
* '''/IRQ''' : Interrupt request input. Input a low state to trigger an interrupt to the CPU. Can only be connected to an open collector cartridge output (there is an internal pullup resistor in the NES/Famicom). Can be left floating if interrupts aren't used.


* '''Audio Out''' : Audio output from the sound generation hardware, already amplified. Only exists with 60-pins connectors.
* '''Audio Out''' : Audio output from the sound generation hardware, already amplified. Only exists with 60-pins connectors.


* '''Audio In''' : Usually just tied with audio out, this one goes directly to the sound output of the console. This allows cartriges to mix audio with their own audio sources. Not directly present on 72-pins connectors.
* '''Audio In''' : Usually just tied with audio out, this one goes directly to the sound output of the console. This allows cartridges to mix audio with their own audio sources. Not directly present on 72-pins connectors.


* '''EXP0..9''' : Pins that goes to the [[NES Expansion Port Pinout|expansion port]] on the bottom of the NES units (not present on Famicoms). Have various uses.
* '''EXP0..9''' : Pins that goes to the [[NES Expansion Port Pinout|expansion port]] on the bottom of the NES units (not present on Famicoms). Have various uses.
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* '''EXP 2''' : Used by some Famicom to NES converters as audio input, because this pin is just straight ahead of the Audio In pin. The NES have to be modified to actually mix that audio with the normal audio.
* '''EXP 2''' : Used by some Famicom to NES converters as audio input, because this pin is just straight ahead of the Audio In pin. The NES have to be modified to actually mix that audio with the normal audio.


* '''EXP 5''' : Used by [[MMC5]] cartridges as an open emmiter input to the cartridge. Output a high state to this pin will force the PRG RAM to be transparent to all reads from it, bypassing any state of the MMC5. Writes aren't disabled in this mode, though. Leave this pin unconnected or tie it to ground will have the PRG RAM working normally (MMC5 carts have their internal pulldown resistor). Only a device that plugs in the expansion port under the NES could make an use of this pin.
* '''EXP 5''' : Used by [[MMC5]] cartridges as an open emitter input to the cartridge. Output a high state to this pin will force the PRG RAM to be transparent to all reads from it, bypassing any state of the MMC5. Writes aren't disabled in this mode, though. Leave this pin unconnected or tie it to ground will have the PRG RAM working normally (MMC5 carts have their internal pulldown resistor). Only a device that plugs in the expansion port under the NES could make an use of this pin.


* '''EXP 6''' : Used by MMC5 cartridges as a Audio In pin. A device that plug-ins on the expansion port under the NES could allow those cartridge to use the [[MMC5 Audio]] on a NES without using a screwdriver.
* '''EXP 6''' : Used by MMC5 cartridges as a Audio In pin. A device that plug-ins on the expansion port under the NES could allow those cartridge to use the [[MMC5 Audio]] on a NES without using a screwdriver.


* '''CHR /WR''' : Also called /WE in official docs. This signal is low when the PPU is writing. On it's falling edge, the adress and data are stable.
* '''CHR /WR''' : Also called /WE in official docs. This signal is low when the PPU is writing. On it's falling edge, the address and data are stable.


* '''CHR /RD''' : Also called plain /RD in official docs. This signal is low when the PPU is reading. On it's falling edge, the adress are stable, and the data should be stable until it's rising edge.
* '''CHR /RD''' : Also called plain /RD in official docs. This signal is low when the PPU is reading. On it's falling edge, the address are stable, and the data should be stable until it's rising edge.


* '''CHR A0..A13''' : Also called PA0..15 in official docs, or PPU A0..15 not to confuse with adress outputs of mappers sharing the same numbers. This is the PPU's adress bus. Note that A13 is typically used to enable CHRROMs and CHRRAMs without any extra logic (this will map [[pattern table]]s to $0000-$1FFF).
* '''CHR A0..A13''' : Also called PA0..15 in official docs, or PPU A0..15 not to confuse with address outputs of mappers sharing the same numbers. This is the PPU's address bus. Note that A13 is typically used to enable CHRROMs and CHRRAMs without any extra logic (this will map [[pattern table]]s to $0000-$1FFF).


* '''CHR D0..D7''' : Also called PD0..7 in official doces, or PPU D0..7. This is the PPU's bidirectionnal data bus. Goes high impedence when CHR /RD goes low allowing memory devices to place their data here.
* '''CHR D0..D7''' : Also called PD0..7 in official doces, or PPU D0..7. This is the PPU's bidirectional data bus. Goes high impedence when CHR /RD goes low allowing memory devices to place their data here.


* '''CHR /A13''' : Simply put, this outputs A13 passed trough an inverter. Typically used to map [[nametable]]s and [[attribute table]]s to $2000-$3FFF.
* '''CHR /A13''' : Simply put, this outputs A13 passed trough an inverter. Typically used to map [[nametable]]s and [[attribute table]]s to $2000-$3FFF.
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* '''CIRAM /CE''' : Also called VRAM /CS. This signal is used as an input to enable the internal 2k of VRAM (used for name table and attribute tables typically, but could be made for another use). This signal is usually directly connected with CHR /A13, but carts using they own RAM or ROM for name table and attribute tables will have their own logic implemented.
* '''CIRAM /CE''' : Also called VRAM /CS. This signal is used as an input to enable the internal 2k of VRAM (used for name table and attribute tables typically, but could be made for another use). This signal is usually directly connected with CHR /A13, but carts using they own RAM or ROM for name table and attribute tables will have their own logic implemented.


* '''CIRAM A10''' : Also called VRAM A10. This is the 1k bank selection input for internal VRAM. This is used to controll how the name tables are banked, in other word, this selects nametable [[mirroring]]. Connect to CHR A10 for vertical mirroring, CHR A11 is for horizontal mirroring. Connect it to a sofware opperated latch can allow bankswitching of two separate name tables, and more flexible control can be allowed on mappers.
* '''CIRAM A10''' : Also called VRAM A10. This is the 1k bank selection input for internal VRAM. This is used to control how the name tables are banked, in other word, this selects nametable [[mirroring]]. Connect to CHR A10 for vertical mirroring, CHR A11 is for horizontal mirroring. Connect it to a software operated latch can allow bankswitching of two separate name tables, and more flexible control can be allowed on mappers.
[[Category:Pinouts]]
[[Category:Pinouts]]

Revision as of 21:49, 26 January 2010

Pinout of 60-pin Famicom consoles and cartridges

                          -------
               GND     - |01   31| - +5V
               PRG A11 - |02   32| - M2
               PRG A10 - |03   33| - PRG A12
               PRG A9  - |04   34| - PRG A13
               PRG A8  - |05   35| - PRG A14
               PRG A7  - |06   36| - PRG D7
               PRG A6  - |07   37| - PRG D6
               PRG A5  - |08   38| - PRG D5
               PRG A4  - |09   39| - PRG D4
               PRG A3  - |10   40| - PRG D3
               PRG A2  - |11   41| - PRG D2
               PRG A1  - |12   42| - PRG D1
               PRG A0  - |13   43| - PRG D0
               PRG R/W - |14   44| - PRG /CE ( /A15 + /M2 )
               /IRQ    - |15   45| - Audio Out
               GND     - |16   46| - Audio In
               CHR /RD - |17   47| - CHR /WR
               CIRAMA10- |18   48| - CIRAM /CE
               CHR A6  - |19   49| - CHR /A13
               CHR A5  - |20   50| - CHR A7
               CHR A4  - |21   51| - CHR A8
               CHR A3  - |22   52| - CHR A9
               CHR A2  - |23   53| - CHR A10
               CHR A1  - |24   54| - CHR A11
               CHR A0  - |25   55| - CHR A12
               CHR D0  - |26   56| - CHR A13
               CHR D1  - |27   57| - CHR D7
               CHR D2  - |28   58| - CHR D6
               CHR D3  - |29   59| - CHR D5
               +5V     - |30   60| - CHR D4
                          -------

Pinout of 72-pin NES consoles and cartridges

                                 +-------+
                             GND |01   37| SYSTEM CLK
                         PRG A11 |02   38| M2
                         PRG A10 |03   39| PRG A12
                          PRG A9 |04   40| PRG A13 
                          PRG A8 |05   41| PRG A14                   
                          PRG A7 |06   42| PRG D7
                          PRG A6 |07   43| PRG D6
                          PRG A5 |08   44| PRG D5                       
                          PRG A4 |09   45| PRG D4
                          PRG A3 |10   46| PRG D3
                          PRG A2 |11   47| PRG D2
                          PRG A1 |12   48| PRG D1
                          PRG A0 |13   49| PRG D0
                         PRG R/W |14   50| PRG /CE (/A15 + /M2)
                            /IRQ |15   51| EXP 9
                           EXP 0 |16   52| EXP 8
                           EXP 1 |17   53| EXP 7
                           EXP 2 |18   54| EXP 6
                           EXP 3 |19   55| EXP 5
                           EXP 4 |20   56| CHR /WR
                         CHR /RD |21   57| CIRAM /CE
                       CIRAM A10 |22   58| CHR /A13
                          CHR A6 |23   59| CHR A7
                          CHR A5 |24   60| CHR A8
                          CHR A4 |25   61| CHR A9
                          CHR A3 |26   62| CHR A11
                          CHR A2 |27   63| CHR A10
                          CHR A1 |28   64| CHR A12
                          CHR A0 |29   65| CHR A13
                          CHR D0 |30   66| CHR D7
                          CHR D1 |31   67| CHR D6
                          CHR D2 |32   68| CHR D5
                          CHR D3 |33   69| CHR D4
                        SECURITY |34   70| SECURITY
                        SECURITY |35   71| SECURITY
                             +5V |36   72| GND
                                 +-------+

Signal Descriptions

Notice : Unless specified, those signals are from the console's viewpoint. So an input is a signal driven by the cartridge to the console, and an output a signal driven by the console to the cartridge connector.

  • +5V : 5V Power supply from the main voltage regulator.
  • GND : 0V power supply.
  • SYSTEM CLK : Main oscillator frequency output. It is only available on 72-pin connectors, and it's speed varies from NTSC to PAL machines.
  • M2 : Also called PHI2 in official docs. This is the CPU clock output. When this signal is high, this means the PRG bus addresses and datas are on a stable state and can be latched by external hardware. On reads, the data must be stable until this signal goes low.
  • PRG R/W : The Read/Write signal output from the CPU. This signal is high on during CPU reads and low during CPU writes (switches from one mode to another only when M2 is low).
  • PRG A0..A14 : Also called just A0..A14 in official docs, or CPU A0..A14 (to not confuse with address outputs of mappers sharing the same number). This is the CPU address buses. It is stable when M2 is high. Note that A15 exists, but is not directly available on the connector.
  • PRG D0..D7 : Also called just D0..D7 in official docs, or CPU D0..D7. This is the CPU bidirectional data bus. It goes high impedence on reads, allowing external memory chips to place their data here.
  • PRG /CE : Also called /ROMSEL in official docs, to not confuse with PRG /CE output of mappers. This pins outputs logical NAND between M2 and PRG A15. It is low when the CPU reads or writes to $8000-$FFFF and when the address is stable, allowing to enable ROM chips directly. Advanced mappers uses more logic between this pin and the actual PRG /CE (to disable bus conflicts, for example). Using this signal is the only way to determine the state of A15, so it's needed for any mappers doing any address decoding.
  • /IRQ : Interrupt request input. Input a low state to trigger an interrupt to the CPU. Can only be connected to an open collector cartridge output (there is an internal pullup resistor in the NES/Famicom). Can be left floating if interrupts aren't used.
  • Audio Out : Audio output from the sound generation hardware, already amplified. Only exists with 60-pins connectors.
  • Audio In : Usually just tied with audio out, this one goes directly to the sound output of the console. This allows cartridges to mix audio with their own audio sources. Not directly present on 72-pins connectors.
  • EXP0..9 : Pins that goes to the expansion port on the bottom of the NES units (not present on Famicoms). Have various uses.
  • EXP 0 : Used by CopyNES in it's cartridge reprogramming mode.
  • EXP 2 : Used by some Famicom to NES converters as audio input, because this pin is just straight ahead of the Audio In pin. The NES have to be modified to actually mix that audio with the normal audio.
  • EXP 5 : Used by MMC5 cartridges as an open emitter input to the cartridge. Output a high state to this pin will force the PRG RAM to be transparent to all reads from it, bypassing any state of the MMC5. Writes aren't disabled in this mode, though. Leave this pin unconnected or tie it to ground will have the PRG RAM working normally (MMC5 carts have their internal pulldown resistor). Only a device that plugs in the expansion port under the NES could make an use of this pin.
  • EXP 6 : Used by MMC5 cartridges as a Audio In pin. A device that plug-ins on the expansion port under the NES could allow those cartridge to use the MMC5 Audio on a NES without using a screwdriver.
  • CHR /WR : Also called /WE in official docs. This signal is low when the PPU is writing. On it's falling edge, the address and data are stable.
  • CHR /RD : Also called plain /RD in official docs. This signal is low when the PPU is reading. On it's falling edge, the address are stable, and the data should be stable until it's rising edge.
  • CHR A0..A13 : Also called PA0..15 in official docs, or PPU A0..15 not to confuse with address outputs of mappers sharing the same numbers. This is the PPU's address bus. Note that A13 is typically used to enable CHRROMs and CHRRAMs without any extra logic (this will map pattern tables to $0000-$1FFF).
  • CHR D0..D7 : Also called PD0..7 in official doces, or PPU D0..7. This is the PPU's bidirectional data bus. Goes high impedence when CHR /RD goes low allowing memory devices to place their data here.
  • CHR /A13 : Simply put, this outputs A13 passed trough an inverter. Typically used to map nametables and attribute tables to $2000-$3FFF.
  • CIRAM /CE : Also called VRAM /CS. This signal is used as an input to enable the internal 2k of VRAM (used for name table and attribute tables typically, but could be made for another use). This signal is usually directly connected with CHR /A13, but carts using they own RAM or ROM for name table and attribute tables will have their own logic implemented.
  • CIRAM A10 : Also called VRAM A10. This is the 1k bank selection input for internal VRAM. This is used to control how the name tables are banked, in other word, this selects nametable mirroring. Connect to CHR A10 for vertical mirroring, CHR A11 is for horizontal mirroring. Connect it to a software operated latch can allow bankswitching of two separate name tables, and more flexible control can be allowed on mappers.
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