Talk:CPU pinout: Difference between revisions
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:When pin 30's input is "processed" it gets inverted, just like with the /RESET pin (since transistors themselves are active-high) - that signal then gets inverted again (so it's now equal to pin 30's input, normalized) and NORed together with the inverted +RESET signal (so it's also the actual state of the input signal), and that result goes to the M2 pin's output logic; thus, if pin 30 is pulled high, then M2 will '''not''' be tri-stated during RESET. --[[User:Quietust|Quietust]] 20:33, 7 May 2011 (UTC) | :When pin 30's input is "processed" it gets inverted, just like with the /RESET pin (since transistors themselves are active-high) - that signal then gets inverted again (so it's now equal to pin 30's input, normalized) and NORed together with the inverted +RESET signal (so it's also the actual state of the input signal), and that result goes to the M2 pin's output logic; thus, if pin 30 is pulled high, then M2 will '''not''' be tri-stated during RESET. --[[User:Quietust|Quietust]] 20:33, 7 May 2011 (UTC) | ||
::The area where pin 30 goes which I thought was part of the Sprite DMA buffer is actually the logic that controls the R/W pin and the direction of the data pins (it puts the data pins in output mode to handle reading from internal registers), and pulling pin 30 high forces all of $4000-$401F to become internal registers (instead of just $4015). This means that pulling pin 30 high will effectively disable the joypad read ports (but '''not''' the write port) - the read enables will still go low, but the CPU won't get any of the data. I'm guessing the designers figured it'd be simpler to do it that way than to combine the 3 read enable signals for $4018-$401A. --[[User:Quietust|Quietust]] 15:21, 9 May 2011 (UTC) | ::The area where pin 30 goes which I thought was part of the Sprite DMA buffer is actually the logic that controls the R/W pin and the direction of the data pins (it puts the data pins in output mode to handle reading from internal registers), and pulling pin 30 high forces all of $4000-$401F to become internal registers (instead of just $4015). This means that pulling pin 30 high will effectively disable the joypad read ports (but '''not''' the write port) - the read enables will still go low, but the CPU won't get any of the data. I'm guessing the designers figured it'd be simpler to do it that way than to combine the 3 read enable signals for $4018-$401A. --[[User:Quietust|Quietust]] 15:21, 9 May 2011 (UTC) | ||
:::Given Lidnariq's edits to the main article, has this actually been tested and verified against actual hardware? --[[User:Quietust|Quietust]] 19:58, 14 September 2011 (UTC) | |||
== M2 == | == M2 == | ||
M2 goes high 1.5 clock cycles (i.e. three clock ''edges'' from the 21.477272MHz master clock) '''before''' Φ2, but it goes low at the same time as Φ2. | M2 goes high 1.5 clock cycles (i.e. three clock ''edges'' from the 21.477272MHz master clock) '''before''' Φ2, but it goes low at the same time as Φ2. | ||
Revision as of 19:58, 14 September 2011
Pin 30
The signal from pin 30 goes through the exact same "processing" as the chip's /RESET signal, at which point it goes to the output logic for the M2 pin (don't know exactly what it does) and then through an inverter which goes to the enables for $4018-$401A and to some other spots (seemingly related to the data buffer used for Sprite DMA). Bit 7 of the writable register at $401A seems to propagate to numerous locations within the sound channels and thus might be responsible for the observation of all writable registers disappearing. --Quietust 16:49, 29 April 2011 (UTC)
- When pin 30's input is "processed" it gets inverted, just like with the /RESET pin (since transistors themselves are active-high) - that signal then gets inverted again (so it's now equal to pin 30's input, normalized) and NORed together with the inverted +RESET signal (so it's also the actual state of the input signal), and that result goes to the M2 pin's output logic; thus, if pin 30 is pulled high, then M2 will not be tri-stated during RESET. --Quietust 20:33, 7 May 2011 (UTC)
- The area where pin 30 goes which I thought was part of the Sprite DMA buffer is actually the logic that controls the R/W pin and the direction of the data pins (it puts the data pins in output mode to handle reading from internal registers), and pulling pin 30 high forces all of $4000-$401F to become internal registers (instead of just $4015). This means that pulling pin 30 high will effectively disable the joypad read ports (but not the write port) - the read enables will still go low, but the CPU won't get any of the data. I'm guessing the designers figured it'd be simpler to do it that way than to combine the 3 read enable signals for $4018-$401A. --Quietust 15:21, 9 May 2011 (UTC)
- Given Lidnariq's edits to the main article, has this actually been tested and verified against actual hardware? --Quietust 19:58, 14 September 2011 (UTC)
- The area where pin 30 goes which I thought was part of the Sprite DMA buffer is actually the logic that controls the R/W pin and the direction of the data pins (it puts the data pins in output mode to handle reading from internal registers), and pulling pin 30 high forces all of $4000-$401F to become internal registers (instead of just $4015). This means that pulling pin 30 high will effectively disable the joypad read ports (but not the write port) - the read enables will still go low, but the CPU won't get any of the data. I'm guessing the designers figured it'd be simpler to do it that way than to combine the 3 read enable signals for $4018-$401A. --Quietust 15:21, 9 May 2011 (UTC)
M2
M2 goes high 1.5 clock cycles (i.e. three clock edges from the 21.477272MHz master clock) before Φ2, but it goes low at the same time as Φ2.
