Talk:APU Frame Counter

The frame counter on the die (upper-right, just below the joypad strobe pin) seems to be a 15-bit linear feedback shift register (with taps at the 14th and 15th bits); when the LFSR is initialized with all 1s and clocked every other CPU cycle, a decoder appears to generate signals at 7456, 14912 (+7456), 22370 (+7458), 29828 (+7458), and 37280 (+7452) cycles. I have not yet determined how these relate to the 2 different sequence modes. --Quietust 17:09, 23 January 2011 (UTC)

Both the 4th and 5th stages (29828 and 32780) trigger the "quarter" and "half" frame signals and reset the LFSR, but the 4th stage is skipped entirely if it's in the 5-step sequence mode. The decode table also has a special case - when all of the bits are 0, it forces 1 into the LFSR's input, presumably to prevent it from stalling (likely triggered on power-up). I can also see some logic that looks like it'll forcefully clock the "quarter" and "half" frame signals upon writing $4017 if D7 is set, which would probably explain the behavior observed (but also result in slightly different timing between the first loop and subsequent loops). --Quietust 15:46, 10 May 2011 (UTC)

When writing to $4017, the frame counter reset and the quarter/half frame triggers happen simultaneously, but only on "odd" cycles (and only after the first "even" cycle after the write occurs) - thus, it happens either 2 or 3 cycles after the write (i.e. on the 2nd or 3rd cycle of the next instruction). --Quietust 18:41, 29 June 2011 (UTC)

With your permission, Quietust, I'd like to incorporate this information into the article. --Drag 22:38, 11 July 2011 (UTC)

Most of it already has been added. --Quietust 13:07, 12 July 2011 (UTC)

My emu doesn't pass in the blargg's frame IRQ flag test if the IRQ is set at 29828, which should be at 29829. Plus, the step 4 reset should be 29831 minus 29828, and not a wrap to zero. What do you think? --Zepper 17:39, 12 July 2011 (UTC)

Perhaps your emulator has issues with interrupt latency? Also, once your counter reaches 29828, it should reset to zero after two cycles - the actual counter in the APU is only updated every other CPU cycle, and when it reaches 14914 (step 4) it resets to 0 instead of incrementing to 14915 (but it isn't really incrementing, since it's a linear feedback shift register as mentioned above). --Quietust 19:33, 12 July 2011 (UTC)

It should also be noted that APU cycles happen when M2 is low - since CPU reads and writes happen when M2 is high, this means that APU cycles and APU writes can never happen at exactly the same time. --Quietust 03:20, 13 July 2011 (UTC)