CPU Test Mode: Difference between revisions

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(APU test mode is only present in the 2A03G (and possibly some earlier revisions), and the IRQ counter was only present in the original 2A03 (where pin 30 did nothing at all).)
(Add this. How exactly does W$401A's lock work?)
Line 1: Line 1:
Pin 30 of the 2A03 revision G can be activated to enable a special test mode for the APU. This activates registers for testing the APU at $4018-$401A at the expense of deactivating the joypad input registers at $4016-$4017.
== 2A03E / 2A03G Test Mode ==
Pin 30 of the 2A03 revision G can be activated to enable a special test mode for the APU. This activates registers for testing the APU at $4018-$401A at the expense of deactivating the joypad input registers at $4016-$4017:
R$4018: [BBBB AAAA] - current instant DAC value of B=pulse2 and A=pulse1 (either 0 or current volume)
R$4019: [NNNN TTTT] - current instant DAC value of N=noise (either 0 or current volume) and T=triangle (anywhere from 0 to 15)
R$401A: [.DDD DDDD] - current instant DAC value of DPCM channel
W$401A: [L..T TTTT] - "lock channel output" and set current instant phase of triangle
                      (What is the polarity of L? How does it work?)


The schematic for the [//nesdev.org/Playchoice.pdf Playchoice 10] implies that this functionality is also in the 2A03E. There it is used by the supervisor CPU to lock out controller input until coins are given to the arcade machine.
== 2A03letterless Programmable Interval Timer ==
Visual inspection of the original 2A03 revision indicates there was planned IRQ functionality from $401C-$401F, but this was left unfinished and unusable and was outright removed from later CPU revisions.
Visual inspection of the original 2A03 revision indicates there was planned IRQ functionality from $401C-$401F, but this was left unfinished and unusable and was outright removed from later CPU revisions.
W$401C,D,E: write lower, middle, upper bits of counter reload value
R$401C,D,E: read lower, middle, upper bits of current counter value
W$401F: [ELAC DTZC]
          |||| ||||
          |||+----+-- Clock source
          |||  |||    00: M2÷16  10: M2÷256
          |||  |||    01: Rising edges of JOY2  10: Falling edges of JOY2
          |||  ||+--- Exists but does nothing. Toggles (invisibly) on terminal count.
          |||  |+---- Value driven out on JOY1. Toggles on terminal count.
          |||  +----- 1:count up; 0:count down
          ||+-------- 1:automatic reload when counter reaches 0
          |+--------- 1:reload immediately
          +---------- 1:IRQ enabled (counts regardless)
R$401F: [E... ...I]
          |      |
          |      +-- Timer IRQ would be asserted if enabled
          +---------- IRQ is enabled
        Reads from $401F acknowledge the IRQ


== See also ==
* Forum: [http://forums.nesdev.org/viewtopic.php?f=9&t=9197 Breaking NES apart (WARNING: traffic)]
* Forum: [http://forums.nesdev.org/viewtopic.php?f=9&t=9197 Breaking NES apart (WARNING: traffic)]
* Forum: [http://forums.nesdev.org/viewtopic.php?f=9&t=14421 Memory map and 2A03 register map / 2A03 cutting-room floormetal]
* Forum: [http://forums.nesdev.org/viewtopic.php?f=9&t=14421 Memory map and 2A03 register map / 2A03 cutting-room floormetal]
* See: [[:File:Apu address.jpg]]
* See: [[:File:Apu address.jpg]]
* See: [[CPU pin out and signal description]]
* See: [[CPU pin out and signal description]]

Revision as of 17:34, 4 September 2018

2A03E / 2A03G Test Mode

Pin 30 of the 2A03 revision G can be activated to enable a special test mode for the APU. This activates registers for testing the APU at $4018-$401A at the expense of deactivating the joypad input registers at $4016-$4017:

R$4018: [BBBB AAAA] - current instant DAC value of B=pulse2 and A=pulse1 (either 0 or current volume)
R$4019: [NNNN TTTT] - current instant DAC value of N=noise (either 0 or current volume) and T=triangle (anywhere from 0 to 15)
R$401A: [.DDD DDDD] - current instant DAC value of DPCM channel
W$401A: [L..T TTTT] - "lock channel output" and set current instant phase of triangle
                      (What is the polarity of L? How does it work?)

The schematic for the Playchoice 10 implies that this functionality is also in the 2A03E. There it is used by the supervisor CPU to lock out controller input until coins are given to the arcade machine.

2A03letterless Programmable Interval Timer

Visual inspection of the original 2A03 revision indicates there was planned IRQ functionality from $401C-$401F, but this was left unfinished and unusable and was outright removed from later CPU revisions.

W$401C,D,E: write lower, middle, upper bits of counter reload value
R$401C,D,E: read lower, middle, upper bits of current counter value
W$401F: [ELAC DTZC]
         |||| ||||
         |||+----+-- Clock source
         |||  |||    00: M2÷16   10: M2÷256
         |||  |||    01: Rising edges of JOY2  10: Falling edges of JOY2
         |||  ||+--- Exists but does nothing. Toggles (invisibly) on terminal count.
         |||  |+---- Value driven out on JOY1. Toggles on terminal count.
         |||  +----- 1:count up; 0:count down
         ||+-------- 1:automatic reload when counter reaches 0
         |+--------- 1:reload immediately
         +---------- 1:IRQ enabled (counts regardless)
R$401F: [E... ...I]
         |       |
         |       +-- Timer IRQ would be asserted if enabled
         +---------- IRQ is enabled
        Reads from $401F acknowledge the IRQ

See also