View source for Fixed cycle delay

== Delay code ==

Shortest possible CPU code that creates N cycles of delay, depending on constraints.

All branch instructions assume that no page wrap occurs.

=== 0 cycles ===
0 bytes

=== 1 cycle ===
Impossible

=== 2 cycles ===
1 byte: <code>NOP</code>

=== 3 cycles ===

If you can clobber S:<br>
1 byte: <code>PHA</code>

If you have a zeropage address that you can write random data into (example: $00):<br>
2 bytes: <code>STA $00</code>

If you can use unofficial opcodes:<br>
2 bytes: <code>NOP $00</code> (04 00)

If you can clobber Z, N and V:<br>
2 bytes: <code>BIT $00</code>

If you can clobber Z, N and A:<br>
2 bytes: <code>LDA $00</code>

Else:<br>
3 bytes: <code>JMP * + 3</code>

=== 4 cycles ===
If you can clobber Z, N, S and A:<br>
1 byte: <code>PLA</code>

If you can use unofficial opcodes:<br>
2 bytes, 1 instruction: <code>NOP $00,X</code> (14 00)

Else:<br>
2 bytes, 2 instructions: 2 × <code>NOP</code>

=== 5 cycles ===
3―4 bytes: <code>NOP</code> + {3-cycle delay code}

=== 6 cycles ===
3 bytes: 3 × <code>NOP</code>

=== 7 cycles ===
2 bytes: <code>PHP<br>
PLP</code>

=== 8 cycles ===
If you can clobber Z, N, S and A:<br>
2 bytes: 2 × <code>PLA</code>

If you can clobber Z, N, X and A:<br>
3 bytes: <code>TSX<br>
PLA<br>
TXS</code>

Else:<br>
4 bytes: 4 × <code>NOP</code>

=== 9 cycles ===
3 bytes: {7-cycle delay code} + {2-cycle delay code}

=== 10 cycles ===

If you can clobber S:<br>
3 bytes: <code>PHA
PHP
PLP</code>

Else:<br>
4 bytes: <code>PHP
BIT $00
PLP</code>

=== 11 cycles ===
3―4 bytes: {7-cycle delay code} + {4-cycle delay code}

=== 12 cycles ===
If you know a memory address that contains byte $60 (<code>RTS</code>):<br>
3 bytes: <code>JSR location</code>

If you can clobber Z, N, S and A:<br>
3 bytes: 3 × <code>PLA</code>

If you can clobber Z and N (note that this does not change C or memory, and that it does not depend on value of X):<br>
4 bytes: <code>ROL $00,X<br>
ROR $00,X</code>

Else:<br>
5―6 bytes: {7-cycle delay code} + {5-cycle delay code}

=== 13 cycles ===
5 bytes: {7-cycle delay code} + {6-cycle delay code}

=== 14 cycles ===
If you know a memory address that contains a harmless 2-cycle instruction that fits your constraints (such as <code>CLC</code>, <code>LDA #0</code>, or <code>NOP</code>), followed by <code>RTS</code>:<br>
3 bytes: <code>JSR location</code>

Else:<br>
4 bytes: 2 × {7-cycle delay code}

=== 15 cycles ===
If you know a memory address that contains a <code>JMP</code> that jumps to another location that contains <code>RTS</code>:<br>
3 bytes: <code>JSR location</code>

If you know a memory address that contains a harmless 3-cycle instruction that fits your constraints (such as <code>LDA $00</code>), followed by <code>RTS</code>:<br>
3 bytes: <code>JSR location</code>

Else:<br>
4―6 bytes: {8-cycle delay code} + {7-cycle delay code}

=== 16 cycles ===
If you can clobber Z, N, S and A:<br>
4 bytes: 4 × <code>PLA</code>

Else:<br>
4―5 bytes: {14-cycle delay code} + {2-cycle delay code}

=== 17 cycles ===
If your 15-cycle delay code is 3 bytes long:<br>
4 bytes: {15-cycle delay code} + {2-cycle delay code}

Else:<br>
5―7 bytes: {10-cycle delay code} + {7-cycle delay code}

=== 18 cycles ===
5―6 bytes: {16-cycle delay code} + {2-cycle delay code}

=== 19 cycles ===
5―8 bytes: {12-cycle delay code} + {7-cycle delay code}

=== 20 cycles ===
If you can clobber Z, N, S and A:<br>
5 bytes: 5 × <code>PLA</code>

If your 18-cycle delay code is 5 bytes long:<br>
6 bytes: {18-cycle delay code} + {2-cycle delay code}

Else:<br>
7 bytes: {13-cycle delay code} + {7-cycle delay code}

=== 21 cycles ===
If your 14-cycle delay code is 3 bytes long:<br>
5 bytes: {14-cycle delay code} + {7-cycle delay code}

If you can clobber Z, N and <index register> (here, assumes X):<br>
5 bytes: <code>LDX #4<br>
loop: DEX<br>
BNE loop</code>

Else:<br>
6 bytes: {14-cycle delay code} + {7-cycle delay code}

=== 22 cycles ===

If you can clobber Z, N and <index register> (here, assumes X):<br>
6 bytes: <code>LDX #3<br>
loop: NOP<br>
DEX<br>
BNE loop</code>

Else:
6―8 bytes: {15-cycle delay code} + {7-cycle delay code}

=== 23 cycles ===
If your 16-cycle delay code is 4 bytes long:<br>
6 bytes: {16-cycle delay code} + {7-cycle delay code}

If your 21-cycle delay code is 5 bytes long:<br>
6 bytes: {21-cycle delay code} + {2-cycle delay code}

Else:
6―7 bytes: {15-cycle delay code} + {7-cycle delay code}

=== 24 cycles ===
If you can clobber Z, N, S and A:<br>
6 bytes: 6 × <code>PLA</code>

If your 17-cycle delay code is 4 bytes long:<br>
6 bytes: {17-cycle delay code} + {7-cycle delay code}

Option:<br>
7―9 bytes: {22-cycle delay code} + {2-cycle delay code}

Option:<br>
7―9 bytes: {17-cycle delay code} + {7-cycle delay code}


== More ==
Bisqwit's 6502 delay_n macro set for ca65: http://bisqwit.iki.fi/src/6502-inline_delay.7z